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a61l73081 series 128k x 8 bit high speed cmos sram (april, 2001, version 1.0 ) amic technology, inc. document title 128k x 8 bit high speed cmos sram revision history rev. no. history issue date remark 0.0 initial issue july 14, 2000 preliminary 1.0 change i cc1 from 120ma to 220ma april 26, 2001 final 100ma to 210ma change i sb1 from 8ma to 12ma change i cdr fro m 1ma to 5ma final spec. release
a61l73081 series 128k x 8 bit high speed cmos sram (april, 2001, version 1.0 ) 1 a mic technology, inc. features n center power pinout n supply voltage: 3.3v 10% n access times: 12/15 ns (max.) n current: operating: - 12: 220ma (max.) - 15: 210ma (max.) standby: ttl: 25ma (max.) cmos: 12ma (max.) n full static operation, no clock or refreshing required n all inputs and outputs are directly ttl compatible n common i/o using three - state output n data retention voltage: 2v (min.) n available in 32 - pin 300mil / 400mil soj packages general description the a61l73081 is a high - speed 1,048,576 - bit static random access memory organized as 131,072 words by 8 bits and operates on a 3.3v power supply. it is built using high performance cmos process. inputs and three - state outputs are ttl compatible and allow for direct interfacing with com mon system bus structures. minimum standby power is drawn by this device when chip enable is disable, independent of the other input levels. data retention is guaranteed at a power supply voltage as low as 2v. pin configurations n soj a0 a2 a3 i/o 0 i/o 1 vcc gnd i/o 2 i/o 3 a4 a5 a6 a8 a7 a9 a10 a11 a12 i/o 5 i/o 6 i/o 7 a14 a15 a16 gnd a61l73081s(sw) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vcc i/o 4 oe a1 ce we a13
a61l73081 series (april, 2001, version 1.0 ) 2 amic technology, inc. block diag ram pin descriptions ? soj pin no. symbol description 1 - 4, 13 - 21, 29 - 32 a0 - a16 address inputs 6 - 7, 10 - 11, 22 - 23, 26 - 27 i/o 0 - i/o 7 data inputs/outputs 5 ce chip enable 28 oe output enable 12 we write enable 8, 24 vcc power supply 9, 25 gnd ground address decoder 1,048,576-bit memory array i/o control control logic a16 a0 oe we 8 8 8 i/o 0 - i/o 7 ce
a61l73081 series (april, 2001, version 1.0 ) 3 amic technology, inc. recommended dc operating conditions (t a = 0 c to + 70 c) symbol parameter min. typ. max. unit vcc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.2 - vcc + 0.5 v v il input low (1) voltage - 0.5 0 +0.8 v c l output load - - 30 pf absolute maximum ratings* vcc to gnd . . . . . . . . . . . . . . . . . . . . . . . - 0.5v to +4.6v in, in/out volt to gnd . . . . . . . . . . - 0.5v to vcc +0.5v operating tem perature, topr . . . . . . . . . . . 0 c to +70 c storage temperature, tstg . . . . . . . . . . - 55 c to +125 c temperature under bias, tbias . . . . . . . . - 10 c to +85 c power dissipation, p t . . . . . . . . . . . . . . . . . . . . . . . 0.7w *comm ents stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational secti ons of this specification is not implied or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (t a = 0 c to + 70 c, vcc = 3.3v 10%, gnd = 0v) symbol paramet er a61l73081 - 12 a61l73081 - 15 unit conditions min. max. min. max. ? i li ? input leakage - 2 - 2 m a v in = gnd to vcc ? i lo ? output leakage - 2 - 2 m a ce = v ih , oe = v ih v i/o = gnd to vcc i cc1 (2) dynamic operating current - 220 - 210 ma ce = v il , i i/o = 0 ma min. cycle, duty = 100% i sb - 25 - 25 ma ce = v ih i sb1 standby power supply current - 12 - 12 ma ce 3 vcc - 0.2v, v in 3 vcc - 0.2v or v in 0.2v v ol output low voltage - 0.4 - 0.4 v i ol = 8 ma v oh output high voltage 2.4 - 2.4 - v i oh = - 4 ma notes: 1. v il = - 3.0v for pulses less than 20 ns. 2. i cc1 is dependent on output loading, cycle rates, and read/write patterns.
a61l73081 series (april, 2001, version 1.0 ) 4 amic technology, inc. truth table mode ce oe we i/o operation supply current standby h x x high z i sb , i sb1 output disable l h h high z i cc1 read l l h d out i cc1 write l x l d in i cc1 note: x = h or l capacitance (t a = 25 c, f = 1.0mhz) symbol parameter min. max. unit conditions c in * input capacitance - 8 pf v in = 0v c i/o * input/output capacitance - 8 pf v i/o = 0v * these parameters are sampled and not 100% tested. ac characteristics (t a = 0 c to +70 c, vcc = 3.3v 10%) symbol parameter a61l73081 - 12 a61l73081 - 15 unit min. max. min. max. read cycle t rc re ad cycle time 12 - 15 - ns t aa address access time - 12 - 15 ns t ace chip enable access time - 12 - 15 ns t oe output enable to output valid - 6 - 8 ns t clz chip enable to output in low z 3 - 3 - ns t olz output enable to output in low z 0 - 0 - ns t chz chip disable output in high z 0 6 - 8 ns t ohz output disable to output in high z 0 6 0 8 ns t oh output hold from address change 3 - 3 - ns
a61l73081 series (april, 2001, version 1.0 ) 5 amic technology, inc. ac characteristics (continued) symbol parameter a61l73081 - 12 a61l73081 - 15 unit min. max. mi n. max. write cycle t wc write cycle time 12 - 15 - ns t cw chip enable to end of write 10 - 12 - ns t as address setup time of write 0 - 0 - ns t aw address valid to end of write 10 - 12 - ns t wp write pulse width 10 - 12 - ns t wr write recovery time 0 - 0 - ns t whz write to output in high z 0 6 0 8 ns t dw data to write time overlap 6 - 7 - ns t dh data hold from write time 0 - 0 - ns t ow output active from end of write 3 - 3 - ns notes: t chz , t ohz and t whz are defined as the time at which the out puts achieve the open circuit condition and are not referred to output voltage levels. timing waveforms read cycle 1 (1) t rc address d out t aa t oe t olz 5 t ace t clz 5 t chz 5 t oh oe t ohz 5 ce
a61l73081 series (april, 2001, version 1.0 ) 6 amic technology, inc. timing waveforms (continued) read cycle 2 (1, 2, 4) t rc t oh t aa t oh address d out read cycle 3 (1, 3 , 4,) t clz 5 t ace t chz 5 d out ce notes: 1. we is high for read cycle. 2. device is continuously enabled, ce = v il . 3. address valid prior to or coincident with ce transition low. 4. oe = v il . 5. transition is measured 200mv from steady state. this parameter is sampled and not 100% tested.
a61l73081 series (april, 2001, version 1.0 ) 7 amic technology, inc. timing waveforms (continued) write cycle 1 (6) (write enable controlled) t wc address d in t ow 7 t dh t dw t whz 7 t wp 2 t as 1 (4) t cw 5 t aw t wr 3 d out we ce write cycle 2 (chip en able controlled) t wc address d in t dw t whz t aw t wr 3 d out t dh (4) t wp 2 t cw 5 t as 1 ce we notes: 1. t as is measured from the address valid to the beginning of write. 2. a write occurs during the overlap (t wp ) of a low ce and a low we . 3. t wr is measure d from the earliest of ce or we going high to the end of the write cycle 4. if the ce low transition occurs simultaneously with the we low transition or after the we transition, outputs remain in a high impedance state. 5. t cw is measured from the later of ce going low to the end of write. 6. oe is continuously low. ( oe = v il ) 7. t ransition is measured 200mv from steady state. this parameter is sampled and not 100% tested.
a61l73081 series (april, 2001, version 1.0 ) 8 amic technology, inc. ac test conditions input pulse levels 0v to 3.0v input rise and fall time 3 ns input and output timing reference levels 1.5v output load see figures 1 and 2 * including scope and jig. 3.3v data out 5pf* 317 w 351 w z o =50 w output r l =50 w v t =1.5v figure 1. output load figure 2. output load for t clz , t olz , t chz , t ohz , t whz , and t ow data retention characteristics (t a = 0 c to 70 c) symbol parameter min. max. unit conditions v dr vcc for data retention 2 3.6 v ce 3 vcc - 0.2v i ccdr data retention current - 5 ma vcc = 2.0v ce 3 vcc - 0.2v v in 3 vcc - 0.2v or v in 0.2v t cdr chip disable to data retention time 0 - ns see retention waveform t r operation recove ry time t rc * - ms t rc = read cycle time
a61l73081 series (april, 2001, version 1.0 ) 9 amic technology, inc. low vcc data retention waveform vcc ce t cdr v ih 3.0v t r v ih 3.0v data retention mode v dr 3 > 2.0v ce 3 > v dr - 0.2v ordering information part no. access time (ns) operating current max. (ma) cmos standby max. (ma) package a61l73081s - 12 32l 300mil soj a61l73081sw - 12 12 220 12 32l 400mil soj a61l73081s - 15 32l 300mil soj a61l73081sw - 15 15 210 12 32l 400mil soj
a61l73081 series (april, 2001, version 1.0 ) 10 amic technology, inc. package information soj 32l(300mil) outline dimensions unit: inches/mm dimensions in inches dimensions in mm symbol min nom m ax min nom max a 0.128 0.132 0.140 3.25 3.35 3.56 a 1 0.052 - - 2.08 - - a 2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.020 0.41 0.46 0.51 b 1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.006 0.008 0.012 0.15 0.20 0.30 d 0.820 0.825 0.830 20.83 20.96 21. 08 e 0.330 0.335 0.340 8.39 8.51 8.63 e 1 0.295 0.300 0.305 7.49 7.62 7.75 e 2 0.260 0.267 0.274 6.61 6.78 6.96 e - 0.050 - - 1.27 - s - - 0.048 - - 1.22 y - - 0.004 - - 0.10 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash. package information 1 a 1 a 2 a e e 2 c 16 17 32 s seating plane d y b 1 b e 1 d min 0.025" 0.004 e y y
a61l73081 series (april, 2001, version 1.0 ) 11 amic technology, inc. soj 32l (400mil) outline dimensions unit: inches/mm dimensions in inche s dimensions in mm symbol min nom max min nom max a 0.131 0.138 0.145 3.33 3.51 3.68 a 1 0.082 - - 2.08 - - a 2 0.105 0.110 0.115 2.67 2.79 2.91 b 0.016 0.018 0.020 0.41 0.46 0.51 b 1 0.026 0.028 0.032 0.66 0.71 0.81 c 0.006 0.008 0.011 0.15 0.20 0.28 d 0.8 20 0.825 0.830 20.83 20.96 21.08 e 0.435 0.440 0.445 11.05 11.18 11.31 e 1 0.395 0.400 0.405 10.03 10.16 10.29 e 2 0.360 0.370 0.380 9.15 9.40 9.65 e - 0.050 - - 1.27 - s - - 0.045 - - 1.14 y - - 0.004 - - 0.10 q - 5 2 6 - 5 2 6 notes: 1. the ma ximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension e 1 is for pc board surface mount pad pitch design reference only. 4. dimension s includes end flash. 1 a 1 a 2 a e e 2 c 16 17 32 s seating plane d y b 1 b e 1 d min 0.025" 0.004 e y y q

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